1. Field of the Invention
The present invention relates to flash memory devices, methods for their operation, and systems incorporating such devices, and more specifically to pipelined burst read functionality for such devices, methods, and systems.
2. Description of the Related Art
Flash memory is a type of nonvolatile rewritable memory useful in a wide variety of digital data applications that require occasional writing and/or rewriting of data, nonvolatile storage, and relatively high-speed read capability. To increase the read speed capability, some flash memory devices include a “burst-read” or “page-read” operation. A flash memory device with this capability responds to a read request by reading a “page” of memory into an on-chip buffer, and then outputting successive data elements from this buffer in response to a group of sequential read pulses.
The burst read operation can be better understood with reference to FIGS. 1 and 2. FIG. 1 illustrates a basic flash memory system 20, including a memory controller 100 and a NAND flash memory device 200. Memory controller 100 supplies control signals CE#, RE#, WE#, CLE, and ALE to memory device 200. Memory controller 100 and memory device 200 also share a bi-directional input/output (I/O) bus, shown in FIG. 1 as a group of eight signal lines I/O0–I/O7. Memory device 200 also drives an R/B# signal to memory controller 200. Of course, other implementations can have different signal lines, bus widths, and/or incorporate multiple flash memory devices, but FIG. 1 illustrates basic concepts found in flash memory systems. Memory controller 100 may be a dedicated circuit or integrated into a larger circuit with additional functionality, such as a digital processor.
The control signals shown in FIG. 1 operate as follows, where “#” indicates a signal that is asserted at a logic low level. Chip enable signal CE# provides selection control: other signals can be routed to multiple memory devices, and the only device that will respond is the one to which memory controller 100 asserts CE#. Read enable signal RE# actually causes memory device 200 to drive read data onto the I/O bus when asserted. Write enable signal WE# causes memory device 200 to latch address, command, or write data off of the I/O bus on a positive transition. Command latch enable signal CLE, when asserted, causes data latched at the memory device's I/O port to be interpreted as a command. Likewise, address latch enable signal ALE, when asserted, causes data latched at the memory device's I/O port to be interpreted as address data.
Input/output signals I/O0–I/O7 are driven by memory controller 100 to transfer commands, address, and write data to memory device 200. In a read operation, I/O0–I/O7 are driven by memory device 200 to transfer read data to memory controller 100. When memory controller 100 and flash memory device 200 are not driving the I/O bus, they each place their respective drivers in a high-impedance (high-z) state.
Finally, flash memory device 200 has the capability to drive ready/busy signal R/B# to memory controller 100. Memory device 200 pulls this signal low when it is programming, erasing, or reading from the memory array.
FIG. 2 contains a timing diagram for the data transfer portion of a data read operation for system 20. Just prior to the time period depicted in FIG. 2, memory controller 100 commands memory device 200 to read data for a specific page of its memory. Flash memory device 200 pulls R/B# low while the specific page is accessed from the memory array to indicate that it is busy. When R/B# returns to a high state, memory controller 100 is permitted to take RE# low (while CE# is low) to cause memory device 200 to drive a first data element Dout N onto the I/O bus. Memory controller 100 then takes RE# high as it latches Dout N off of the I/O bus. Memory device 200 then returns the I/O bus to a high-z state and awaits a new read cycle.
Several timing parameters dictate how quickly successive reads in a burst can occur. Timing parameter tREA represents the worst-case read-enable-to-access time, i.e., the delay between when memory controller 100 takes RE# low and when memory device 200 begins to drive Dout N onto the I/O bus. Timing parameter tRC represents the shortest read cycle time, i.e., time between successive reads in a burst, that can be supported by the device. Parameter tRC generally has two sub-parameters tRP and tREH as shown. Timing parameter tRP represents the minimum read pulse width, i.e., time between RE# assertion and data latching. Finally, timing parameter tREH represents the RE# high hold time, i.e., the minimum time that memory controller 100 must hold RE# high between successive read pulses.
In general, memory controllers can support a higher bus operating speed than supported by a NAND flash memory, particularly for low-voltage flash memory. A NAND flash memory with a reduced read cycle time would therefore be advantageous in speeding overall system performance. In the conventional approach, the pulse width, tRP, cannot be reduced below the access time tREA or else the memory controller will latch erroneous data before the memory device has driven the requested data to the memory controller.